Stress in thin layers of dielectrics, metals, and other thin material layers deposited on a semiconductor wafer is an important parameter in semiconductor device fabrication. Thin film stress can result in warpage of the wafer which can affect device performance, reliability, and line-width control during various microlithographic patterning steps. In extreme cases, the warpage resulting from thin film stress can present problems in securing and handling the wafer during device processing.
Additionally, various high temperature (e.g. above 850.degree. C.) processes such as rapid thermal processing (RTP), epitaxial growth, thermal oxidation, thermal annealing, and some low-pressure chemical-vapor deposition (LPCVD) processes can result in the formation of slip dislocation lines on the wafer surface, mostly at the wafer edge. The slip dislocations are the result of crystal dislocations in the semiconductor substrate due to temperature non-uniformities causing thermally induced mechanical stresses. Such slip dislocations can reduce device fabrication yield and interfere with microlithography process steps. It is important to have in-situ measurement capability to characterize and quantify stress and slips in order to optimize process/equipment parameters.
Available systems for evaluating thin film stress usually employ a laser beam to measure the wafer warpage (radius of curvature) in order to extract thin film stress values. These systems, however, usually rely on large optical components requiring the systems to be separate from the semiconductor processing equipment. These systems, therefore, cannot be used for in-situ sensing and measurement applications such as those desired for semiconductor manufacturing equipment and process/equipment control and diagnostics. These stress measurement systems are also rather expensive and have been designed exclusively as ex-situ stand-alone measurement and inspection tools. Moreover, the available stress measurement tools only provide an average film stress value for the entire wafer surface and do not provide information on stress distribution.
X-ray topography has been the primary semiconductor characterization technique used for slip dislocation mapping. X-ray topography, however, is an ex-situ material evaluation technique which requires removing the wafer from the semiconductor process equipment. X-ray topography systems are, therefore, ex-situ off-line tools which cannot provide real time in-situ slip dislocation mapping information. X-ray topography systems are also rather expensive. Moreover, x-ray exposure can result in generation of defects in device structure which can cause accelerated aging and poor reliability.